Advanced Encryption Standard (AES) is a symmetric-key encryption protocol that some computing platforms use to encrypt and decrypt all read/write hard drive accesses. In order to prevent such reads/writes from swamping processor performance, hardware acceleration of AES encrypt/decrypt operations is desirable.
AES provides several modes of operation. AES-128, AES-192 and AES-256 modes of operation submit 128-bit input data to, respectively, 10, 12 and 14 iterations of an AES round operation. The AES round operation includes successive SubstituteByte, ShiftRow and MixColumns transformations, followed by an AddRoundKey operation.
During the SubstituteByte transformation, each 8-bits of the 128-bit input data is input to one of sixteen S-boxes. Each S-box computes the multiplicative inverse of its respective 8-bit input in the Galois Field GF(28). Some implementations map the 8-bit input to a composite field GF(24)2, compute the multiplicative inverse in GF(24)2, map the result back to GF(28), and proceed to the ShiftRow transformation. These existing implementations are unsuitable in terms of silicon footprint, power and/or cycle time.